Generating Optimized Multicore Accelerator Architectures

摘要

Designing multicores architectures to achieve a balance between performance, area and energy efficiency is still a challenge given the large diversity of embedded applications. In this scenario, combining different hardware processing elements at design time to balance the aforementioned constraints is crucial to provide an efficient design. Reconfigurable architectures (RAs) are flexible platforms able to save energy and improve performance due to their reconfiguration and parallelism exploitation capability. However, in order to enhance performance and reduce energy and area, it is necessary to provide optimized designs, choosing among many different processor cores and RAs. In this work, we combine superscalar processors with coarse grained reconfigurable architectures to provide multicores architectures optimized for performance, energy and area under certain constraints. The proposed designs were generated considering three scenarios: highest performance possible for a set of benchmarks; performance threshold limitation and energy budget. We perform a case study varying micro-architectural parameters as processor issue width and CGRA number of functional units. As results of our experiments at a specific evaluated scenario, the optimized generated multicores achieved a speedup up to 2.8x. Additionally, with a reduction of 10% of speedup, it was possible to save more than 11% in energy and with an energy saving budget of 20%, one can save more than 30% in area.