An Efficient VLSI Design of Residue to Binary Converter Circuit for a New Moduli Set {2²ⁿ, 2^2n–1 – 1, 2^2n–1 + 1}

摘要

This paper presents a new 6n bit moduli set {2²ⁿ, 2^2n-1 - 1, 2^2n-1 + 1}, n ≥ 2 with its associated Residue representaion to binary representation arithmetic scheme. After demonstrating that the proposed moduli set is valid for the construction of a Residue Number System Processor, a reverse converter algorithm is presented using the New Chinese Remainder Theorem (CRT) I. Closed forms of multiplicative inverses required for the implementation of the New CRT I are introduced. The resulting architecture is further reduced to obtain an adder based and memory free scheme. Our investigations after implementing the proposed converter and other best known similar state of the art schemes on Xilinx xc6slx45-3fgg484 FPGA shows that on the average, the converter circuit for the new moduli set {2²ⁿ, 2^2n-1 - 1, 2^2n-1 + 1} is more efficient than other similar state of the arts converters in terms of area resource requirement and conversion time.