Implementation of Approximate Adder circuit of Ladner Fischer Adder (16 bit)

摘要

Achieving minimum computation time and reduced power utilization is of great interest in VLSI Design. This paper presents the designing of an approximate adder such as Ladner Fischer with the use of parallel computing. Earlier technologies have used the redundant method of Ripple Carry Adders to perform arithmetic operations but multipliers are an important part of any operational unit which uses large adders in the multiple sequences, and the execution rates should be minimized. The topology implemented in this paper is developed using VHDL, and the functionality is verified using simulation tools such as Genus, Innovus, NC Launch, etc. from Cadence and synthesized to 90 nm CMOS Technology. For 16-bit addition, the current design dynamic power obtained is 0.0187 W and the total area cell covered is 26%.