A Research on SRAM-based FPGA Operating Frequency Margin Test Method

摘要

With the wide application of SRAM-based FPGA, the programmable resources of SRAM-based FPGA and its internal IP core are applied to the maximum extent. Owing to the negative correlation between the FPGA resource utilization and frequency, the FPGA frequency margin becomes a bottleneck that restricts reliable application of FPGA under extreme application conditions. The deviation of the manufacturing process leads to certain discreteness in the frequency after the FPGA chip is assembled and packaged, thus the devices with extremely low frequency shall be removed. In this regard, it is crucial to determine the frequency margin range of SRAM-based FPGA in order for the application reliability. In this paper, simulation and testing of the frequency limits of FPGA are conducted via LUT ring oscillator, carry chain ring oscillator and multiplier core ring oscillator, to analyze the simulation value and measured value, and the difference of the device under test from the products manufactured by Xilinx. The recommended standard for screening of the frequency margin of SRAM-based FPGA is also provided.