Sample and Hold Circuit with Clock Boosting

摘要

Sample and hold circuit is an integral part of analog to digital convertors. In this work different sample and hold circuits are simulated using LTSPICE XVII, in 180nm TSMC technology and their performances are analyzed. The input signal of 250mVP-P and a frequency of 100Hz is used for simulation purpose. It is found that the sample switch with a clock boosting circuit outperforms the other designs. A rail to rail sampling of the input voltage is achieved. Sampling frequency of 2KHz is used. An SNDR of 45.01dB and an average power consumption of 1.036nW are achieved. The sampling switch with clock boosted network can be used as a potential candidate in analog to digital convertor design for low frequency physiological signal.