System Design of ATSC3.0 Broadcast Gateway Based on CPU-FPGA

摘要

According to the latest ATSC3.0 standard, a broadcast gateway software implementation scheme using multi-thread network programming is devised. This scheme meets real-time processing demand of fundamental system capacity. In order to satisfy extension business demand of higher capacity and higher concurrency of future fusion network, a CPU-FPGA software-hardware co-design scheme is proposed in the consideration of data processing features of broadcast gateway. Based on the results of detailed data processing task analysis, the most time consuming and the highest CPU occupation ratio tasks are distributed to FPGA implementation. Data exchange and operation synchronization between software and hardware is realized through data sharing and memory mapping I/O. According to testing results, the time consumption of main modules and the overall CPU occupation ratio are reduced effectively. The data capacity of a broadcast gateway is greatly improved at the same time.