Technology-agnostic power optimization for AES block cipher

摘要

On the one hand, IoT applications require low-power consumption. On the other hand, they also need to embed strong cryptographic algorithms to protect the data they manipulate. We address this issue in the context of the AES block cipher. The challenge is to design an AES module consuming as little as possible, mostly by leveraging on the architecture. This paper presents two contributions. First of all, we present design guidelines for low-power AES, including lazy dataflow, glitch reduction techniques in combinational logic and algebraic simplification of diffusion operations. These optimizations allow to divide by two the power consumption of the AES module. Second, we show a methodology to improve the power consumption using a high-level technology-independent power and security evaluation tool (Virtualyzr).