Stochastic Bounds for Markov Chains on Intel Xeon Phi Coprocessor

摘要

The author presents an approach to find stochastic bounds for Markov chains with the use of Intel Xeon Phi coprocessor. A known algorithm is adapted to study the potential of the MIC architecture in algorithms needing a lot of memory access and exploit it in the best way. The paper also discusses possible sparse matrices storage schemes suitable to the investigated algorithm on Intel Xeon Phi coprocessor. The article shows also results of the experiments with the algorithm with different compile-time and runtime parameters (like scheduling, different number of threads, threads to cores mapping).