Design and Implementation of Credit-Based Dynamic WRR Scheduler For Satellite Onboard Switches

摘要

Considering the hardware resource limitation in satellite onboard switches, a Credit-based Dynamic WRR (CDWRR) Scheduler is presented in this paper. The scheduler can improve the throughput under nonuniform traffics and afford good support for multicast traffics. It can also guarantee the service priority and ensure the fairness concurrently. With the 128 bit data width and 100 MHz system clock, the peak throughput of switch fabric mentioned in this paper is 12.8 Gbps, which can meet the requirement of the 10 Gbps input port for the satellite onboard switches. The CDWRR scheduler is used in a Combined Input Output Queued (CIOQ) switch structure and realized with Verilog HDL. The scheduler occupies 2251 LUTs and 3 Block RAMs in a Xilinx xc6vlxl30t FPGA, which indicates that the key resources consumption can meet the requirements of triple modular redundancy. Typical simulated results show that the scheduler works correctly.