Design and Performance Test of Three Phased Synchronous Reference Frame-Phase Locked Loop (SRF-PLL) using DSPIC30F4011

摘要

Phase Locked Loop (PLL) is widely used for synchronizing between grid-connected inverter systems with the utility grid. Ideally, the PLL should estimate grid voltage information accurately. The aim of this research is to design and implement the popular Synchronous Reference Frame - Phase Locked Loop (SRF-PLL) to estimate phase, magnitude and frequency of the three phase grid voltage. In this work, the PLL algorithm is embedded in the 16 bit wide dsPIC30F4011 microcontroller where the time sampling used to execute the algorithm is 0.1 ms. For analysis purposes, the estimated grid voltage parameters are then sent to DAC AD7302 to observed by oscilloscope. Based on experimental result, the realized algorithm could estimate the three phase grid voltage parameters accurately.