FPGA in the loop implementation of an adaptive-filtering based control of shunt active power filter

摘要

A novel digital filtering algorithm is introduced to enhance the dynamic performance of the conventional SRF harmonic compensation technique. The crucial part in the operation of the SRF method is the DC component extraction of the current. This is usually done using the classical low pass filter. This filter, however, presents a delayed response and a limited effectiveness especially in presence of random and time-varying harmonics. To overcome these limits, the proposed adaptive filter based on VLLMS adaptation allows the improvement of the speed and the accuracy of harmonics estimation. As a result, the performance of the Shunt active power filter is improved allowing effective harmonic mitigation. To validate the results, an FPGA in the loop prototype is simulated using SIMULINK and Altera DE1Soc board. The obtained results present a significant improvement in the dynamic response to less than a quarter of a cycle with reduced hardware resources use.