Design and Implementation of Low Power 6:3 Fast Counter based on Symmetric Stacking

摘要

In modern VLSI Design, low power and high speed are the parameters of utmost importance. This brief presents an efficient implementation of a 6:3 fast counter, a technique of counting which employs bit stacks. Further, an innovative technique is used to form a bigger stack using combination of 2 small stacks. 6:3 counter is built using this technique which has no multiplexers and XOR gates in the critical path. Simulation results are used to verify the advantages of the proposed approach. Further, low power implementation using Switch Rail Charge Recovery Logic (SCRL), a variant of adiabatic logic is done. The 6:3 counter built using symmetric stacking is 21% faster than the traditional counter based on Full adder. Also, it is evident that SCRL achieves a power saving of nearly 79% when compared to the conventional CMOS logic. The overall power delay product of SCRL implementation is 0.161 *10-^{18which is a significant improvement over the traditional implementation.}