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Nested interconnect macro electrical yield improvement for advanced triple patterning integration

机译:嵌套互连宏电产量提高,用于高级三重图案集成

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For metal pitches below 50nm, triple patterning (LELELE) integration is utilized in most advanced technologies to build the Cu interconnect. This integration relies on etch to shrink to the target critical dimension. As a result of high iso-dense bias in conventional etch process, nested serpentine structures formed by different metal colors show massive shorts that limit defect density yield. In this paper, several approaches in improving the isodense bias, as well as improving the nested serpentine electrical yield will be discussed.
机译:对于低于50nm的金属间距,在最先进的技术中采用了三重图案(LELELE)集成来构建Cu互连。这种集成依靠蚀刻缩小到目标临界尺寸。由于常规蚀刻工艺中的高等密度偏压,由不同金属颜色形成的嵌套蛇形结构显示出大量短路,从而限制了缺陷密度的产生。在本文中,将讨论改善等当量偏差以及提高嵌套蛇形电产量的几种方法。

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