A local reconfiguration based scalable fault tolerant many-processor array

摘要

This paper presents a reconfigurable Many-processor Array utilizing a layer of Routers with localized interconnects to provide fault tolerance for Processing Elements (PEs). In such a system, each PE is assigned to a Router in the neighborhood. The required interconnect topology among the PE's is implemented via a fixed Backbone Network connecting all the Routers. A localized Auxiliary Network is used to provide assignment flexibilities between each Router and its peripheral PE's. Faulty PE's are repaired via spare PE's in the array, and to extend the reach of spares, repair is done via Replacement Chains: a faulty PE's Router will be assigned to another functional PE within its neighborhood; the Router of the replacement PE will then be reassigned to another PE, until eventually a spare PE is reached. In this paper, we propose a Many-processor Array on the basis of this principle, and show that this architecture is able to deliver high level of fault tolerance properties while being scalable in hardware and interconnect overheads.