Tessellating memory space for parallel access

摘要

Modern reconfigurable computing chips, such as FPGAs, offer an unprecedented opportunity to achieving both multifunctionality and real-time responsiveness for memory-intensive embedded applications. However, how to cost-effectively synthesize application-specific hardware constructs that fully exploit memory-level parallelism remains to be a key challenge. To address this problem, we propose a new tessellation-based memory partitioning and mapping scheme that aims at maximizing parallel memory accesses while conserving both hardware and energy consumption. Comparing with the existing linear skewing and hyper-plane partitioning methodologies, our proposed technique exploits the regularity of tessellation patterns to assign memory bank and calculate intra-bank offset in a direct geometric-based manner, therefore not only quite intuitive to comprehend, but also quite straightforward to implement with hardware. To empirically validate our proposed tessellation-based methodology, we have implemented a baseline prototype with a standard Virtex 7 FPGA device and the Vivado HLS engine from Xilinx. Our experimental results have shown that on average for 5 benchmark applications from SPEC2006, compared with state-of-art methods, we have improvements in clock period of around 13%, memory overhead reduction of up to 100%, and reduction of DSP usage up to 100%.