On the fault coverage of high-level test derivation methods for digital circuits

摘要

Testing digital circuits is crucial for guaranteeing the correct and reliable functioning of electronic devices. Deriving high quality test suites to check the correctness of such devices is an important task. To estimate the quality of a test suite, a common approach is to simulate faults in a given circuit specification and to assess the fault coverage of the test suite. In this paper, we propose to use test suites derived at a high abstraction level, i.e. using Finite State Machines (FSMs), and to assess its fault coverage for three different types of faults. Those are single stuck-at faults, `bridge' faults, and hardly detectable faults, which slightly modify the behavior of a single circuit gate. A set of tools was developed for this reason, and experimental results were obtained for a set of ITC'99 benchmarks (Second Release). The fault coverage for the proposed approach is over 90% in most of the cases.