Reliability and Power Optimization in 3D-Stacked Cache Using a Run-Time Reconfiguration Procedure

摘要

This paper presents an analytical model for future high performance computing architecture design exploration. We proposed a convex optimization model and applied it as a run-time solution for 3D stacked cache which is designed with volatile STT-RAM. The reconfiguration mechanism is done by a monitor tile placed along each cache banks. Experimental results on PARSEC benchmarks show that the proposed method improves throughput and energy-delay product, in comparison with the baseline architectures with homogeneous cache system.