HCD-Induced GIDL Increase and Circuit Implications

摘要

In this paper we review the physics of gate-induced drain leakage (GIDL) increase due to hot carrier degradation (HCD) and the proposed modelling for reliability simulations. A case study of an analog circuit where this phenomenon leads to an overall increase of static power consumption over time is shown. This is attributed to the GIDL current being the major component of the leakage current of the circuit in off-mode. Finally, we propose some mitigation techniques by using alternative devices including high-K metal gate (HKMG) devices, where the GIDL current does not show uniform behavior post HCD.