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Simulated Dielectric Characteristics of Pt/BST/Ni-Fe/Cu Multilayer Capacitor Stack for Storage Application

机译:PT / BST / NI-FE / CU多层电容器堆栈模拟介电特性,用于存储应用

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摘要

In this simulation research work, the metal-composite-metal (MCM) multilayer capacitor structure [Pt/BST/Ni-Fe/Cu] is proposed with Barium Strontium Titanate (BST) oxide material as the capacitor dielectric material for DRAM with permalloy Nickel-Ferrous (Ni-Fe) coated Copper (Cu) as the bottom conducting electrode and platinum as the top conducting electrode. This proposed MCM consists of 120μm Cu bottom contact material, a 1μm of Ni-Fe alloy over the stoichiometric composition of the BST oxide dielectric material of thickness 40nm and dielectric constant of 775. The MCM structure is expected to deliver a maximum charge storage capacity of 109.75 fF for a capacitor in DRAM cell area of 0.64μm{sup}2 well above the minimum requirement for DRAM cell. The leakage current density for a variation of voltage from 0 to 10V has been simulated for temperature variation. When compared with the previous report, the proposed multi layer capacitor (MLC) structure shows promising potentials in terms of dielectric characteristics.
机译:在该模拟研究工作中,用钛酸锶锶(BST)氧化锶(BST)氧化物材料(BST / BST / Ni-Fe / Cu]作为渗透氧化镍镍的电容器电介质材料提出了金属 - 复合金属(MCM)多层电容器结构[Pt / Bst / Ni-Fe / Cu]作为底部导电电极和铂作为顶部导电电极的 - 配铜(Cu)。该提出的MCM由120μm的Cu底部接触材料组成,在厚度40nm的BST氧化物电介质材料的化学计量组合物上由1μm的Ni-Fe合金组成,介电常数为775。预期MCM结构可提供最大电荷存储容量109.75 FF用于DRAM单元面积0.64μm{sup} 2的电容器,远高于DRAM细胞的最低要求。已经模拟了从0到10V的电压变化的漏电流密度用于温度变化。与先前的报告相比,所提出的多层电容器(MLC)结构在介电特性方面示出了有希望的电位。

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