Real-Time Error Correction of High Speed Time-Interleaved Analog-to-Digital Converters with State of the Art FPGA Technology

摘要

High speed time-interleaved analog-to-digital converters (TIADCs) suffer from gain, offset and timing errors which reduce their effective resolution. By a posterior digital error correction this errors can be corrected. To achieve this, known error models are applied to the converters. Error estimation and error correction approaches are derived from these models. A realization of a digital real-time posterior error estimation and error correction is implemented in VHDL for a 3 to 6 bit analog-to-digital converter with a sampling rate up to 24 GS/s.