A new all-digital phase-locked loop based on single CPLD

摘要

With the development of digital circuit technology, digital phase-locked loop (DPLL) has been widely applied. But regard to the existing DPLL systems, both the range of the locked phase and the running speed can't meet the needs of the application in reality. The heart of the matter is the constraint of algorithm and structure. In order to improve the performance, we present a new all-digital phase-locked loop (ADPLL) in this paper. We adopted frequency tracking algorithm and phase tracking algorithm to composite frequency multiplying signal and phase-locked signal in a way similar to the DDS. All algorithms were loaded into a single CPLD. The CPLD which was customized to a DPLL has a good performance in the tests. Compared to the current ones, this one locks phase faster and the frequency range of the input signal is wider.