Memory bus lines between a controller and frame memories on a TV main board are usually densely packed, which give rise to noise like crosstalk-induced jitter (CIJ), crosstalk-induced glitch (CIG), and(or) reflections. Since these types of noise can substantially limit the data rate between the controller and the frame memory, we may need a larger number of frame memories, an increased printed circuit board (PCB) layout size, and more PCB layers to minimize these noise components, resulting in an increased design cost. To cope with this issue, this work proposes a 1/3 unit interval (UI)-staggering in the transmitter side and a capacitive coupling-induced crosstalk compensation in the receiver side. Evaluation results indicated that CIJ and CIG are reduced by up to 75% and 65% at 1Gbps data rate, respectively. They also indicated that the proposed method enables 5Gbps operation per pin on a frame memory bus for TVs.
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