Insertion sort correction of two-way merge sort algorithm for balancing capacitor voltages in MMC with reduced computational load

摘要

The Modular Multilevel Converter (MMC) is very suitable for high-power applications like High-Voltage Direct Current (HVDC) transmission system, in which the number of submodules is commonly very large to reach high voltage. Therefore, the sorting algorithm of the conventional voltage balancing strategy causes too much computational load, greatly increasing the hardware cost and challenging the controller design. This paper introduces a two-way merge sort that evidently reduces computation weight and accelerates the sorting, combining with the prediction of capacitor voltages in ideal conditions. Furthermore, to solve the issue of non-ideal conditions in practical applications, this paper proposes an insertion sort correction algorithm with little and controllable computational load on the basis of the two-way merge sort. The proposed sorting algorithm takes advantage of the features of MMC control strategy, and consequently is much faster than conventional sorting such as quicksort. 401-level MMC simulation results in PSCAD/EMTDC show the validity of the proposed sorting algorithms, and the reduced computational load with shorter execution time is verified by DSP controller TMS320F28335.