Study of layout extraction accuracy on W/L estimation of ELT in analog design flow

摘要

This paper presents an investigation regarding the model adopted by a commercial layout extraction tool to estimate the aspect ratio (W/L) of enclosed layout transistors (ELT). The method used by the EDA (Electronic Design Automation) tool to obtain an equivalent W/L is compared with well know mathematical models presented on the literature. The influences in the aspect ratio estimation regarding designer-controlled layout variables are also target of investigation. Results indicate that the EDA tool analyzed in this work, overestimates the extraction of aspect ratio from ELT layout, when compared with a more accurate mathematical model used to calculate the effective aspect ratio of square ELT devices. The results also show that designer-controlled layout variables may contribute to increase the divergences among the extraction tool method and the studied models in the estimation of the ELT aspect ratio.