Enhanced implementation of morphological operators on a synthesizable ASIP

摘要

Mathematical morphology operators are applied in many real time applications such as computer vision. Therefore, an efficient hardware implementation is needed to satisfy these real time requirements. In this paper we present an ASIP for basic morphological operations. We propose a modification of HGW algorithm to deal with the Plasma Soft Core processor. The ASIP has been synthesized into a FPGA. It has therefore achieved a high frequency of 137 MHz and processed a speed of 2.88ms with a flat structuring element.