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Design and Implementation a Hierarchical Co-Verification Platform for Gigabit Ethernet Controller of Multi-core Processor

机译:设计与实现多核处理器千兆以太网控制器的分层共同验证平台

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With growing interconnection network technology, Ethernet MAC (Media Access Control) controller integrated in processor chip for their network services has become the trend, This paper studies the design and pre-silicon verification of multi-core processor' Ethernet controller, how to improve the verification efficiency? Test bench validity and completeness is the great challenge of verification work. This paper puts forward the method to generate hierarchical classification and management respectively on verification resources and test bench, proposes a hierarchical software and hardware co-verification platform to verify functionality and preliminary performance evaluation, which improves the efficiency of verification, and accelerates the verification cycle of the target chip, the chip is tape out now.
机译:随着互联网络技术的不断增长的网络技术,以太网MAC(媒体访问控制)控制器集成在处理器芯片的网络服务中已成为趋势,本文研究了多核处理器的以太网控制器的设计和预硅验证,如何提高验证效率?测试工作台有效性和完整性是核查工作的巨大挑战。本文提出了在验证资源和测试台上生成分层分类和管理的方法,提出了分层软件和硬件共同验证平台,以验证功能和初步性能评估,从而提高了验证效率,并加速了验证周期在目标芯片的芯片中,芯片现在是卷尺。

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