Effect of flicker noise on SEIR for accurate ADC linearity testing

摘要

This paper investigates the effectiveness of the stimulus error identification and removal (SEIR) algorithm for linearity testing of high precision Analog-to-Digital Converters (ADCs) in the presence of flicker noise. The SEIR algorithm has been demonstrated to be highly effective in estimating the integral nonlinearity (INL) of high precision ADCs tested with low linearity input sources. Since flicker noise has the tendency to accumulate to large values over time, simulations reveal that this accumulation will introduce errors in linearity estimation when using SEIR. Previously, Center Symmetric Interleaving (CSI) pattern was used for generating input ramps. Both simulations and measurement results have proven its effectiveness in suppressing environmental nonstationarity which is in polynomial form. Simulations of CSI combined with SEIR show that CSI is not effective in eliminating the error in linearity estimation introduced by flicker noise with an rms value of 0.5 LSB, since flicker noise is not in polynomial form. In comparison, simulations with an interleaving pattern, which is easier to implement in practice, show that it is more effective in reducing the estimation error caused by flicker noise. By using 128 triangle waves with 0.15 LSB rms flicker noise, the estimation error can be reduced to within 0.5 LSB.