A novel quarter-rate binary phase detector with inherent De-multiplexer and majority voter

摘要

Increasing requirement for high speed serial links has necessitated a great effort in this field. An important part of a serial link which is its speed bottleneck is clock data recovery circuit. Phase detector is a prominent component in a CDR which is challenging in high speed structures as it samples high speed and mostly distorted received data and decides its phase relation with local clock signal. In this study we propose a binary quarterrate phase detection technique. It uses slope and data detection concept; however, it introduces a novel slope detection technique to alleviate speed limitations of its baud-rate counterparts. Moreover a novel analog majority voting and de-multiplexing features are included in the structure of this phase detector circuit so that wrong decisions are avoided more effectively without any power overhead. Implementing in 0.18 um CMOS technology we present simulation results for 16 Gbps pseudorandom input data.