A methodology for early functional verification of embedded software combining virtual platforms and bounded model checking

摘要

The amount of embedded software present in our daily routines has been increasing with more electronic devices being introduced in many different areas. As a consequence, concerns with safety and reliability has led to the development of a series of mechanisms for verification and design of such systems. Although Bounded model checking (BMC), for example, has received much attention lately, practical use might be restricted, considering systems complexity. In this paper, we show a methodology for combining BMC with Electronic System Level Design and Virtual Platforms. Our approach has the potential to improve system level verification, through simulation, and to accelerate the development process with Virtual Platforms.