The increasing computation requirements of multimedia and streaming applications demand high parallel processing capabilities. Hence modern computer architectures focus on integrating more processing cores into a single chip to achieve higher parallelism and processing capability. These processing cores rely on sophisticated on-chip network to communicate among others. Accordingly, this paper provides a novel on-chip network, called Camellia, for integrating lots of cores into a single chip. The proposed Camellia topology, network components, and routing mechanism can provide high bandwidth, low communicating hop counts, and high scalability interconnection network to integrate processors. The organization of Camellia network is proposed. The results of performance analysis and hardware implementation are also provided.
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