Multiplier-less implementation of quadrature mirror filter

摘要

The minimum hardware and low power dissipation have always been the main concern for the efficient filter implementation. In this paper, an efficient way of implementing the lattice wave digital filter (LWDF) structure of the quadrature mirror filter (QMF) with canonic signed digit (CSD) coefficients is proposed. Further, the proposed structure is implemented using carry save adders rather than slow carry propagation adders. This increases the speed of the overall filter structure compared to the conventional way of implementing the filter with CSD coefficients. The proposed QMF is implemented and successfully tested on Xilinx Spartan XC3s200-4ft256 field programmable gate array (FPGA) device. The effectiveness of the proposed design method is proven with an example.