Stub-series terminated logic based energy Efficient Devnagri Unicode Reader design on 40nm and 28nm FPGA

摘要

It has been observed that amongst all the 22 languages being used Devanagari script is being the primary and most widely used script. Devanagari is used for writing the Hindi language in India. In this paper Energy Efficient Devanagari Unicode Reader has been designed. Devanagari is used for writing the Hindi language in India. In this paper Devanagari Unicode Reader code has been implemented on Xilinx ISE Design Suite 14.2 and the results of 28nm FPGA platform has been compared with the 40nm technology. Impedances of transmission line, port and device should be equal in order to avoid reflection in transmission line which is a usual problem in hardware design. So SSTL logic family has been used at input and output ports so as to avoid such reflections. The power analyses had been done at different frequencies ranging from 1 THZ to 1 MHZ using different IO standards of SSTL logic family. Out of 40nm (Virtex -6) and 28nm(Artix-7),maximum power has been saved in case of 28nm(Artix-7) when the device is operating at frequency of 1MHZ on SSTL18 IOstandard.