Design and implementation of fractional order integrator with reduced hardware

摘要

This paper proposes a novel methodology for design and multiplierless implementation of fractional order integrator (FOI) based on lattice wave digital filter using gravitational search algorithm (GSA). The FOI design problem is formulated as an optimization problem using the transfer function of lattice wave digital filter (LWDF). The realization of FOI using LWDF structure increases the accuracy of design due to its excellent properties and also it requires only N number of multiplier coefficients for Nth order FOI. Furthermore, the minimum hardware and low power dissipation of FOI, which are the main concern of efficient implementation is also presented in this paper. The design level area optimization of the proposed lattice wave digital FOI (LWDFOI) is done by converting constant multipliers into shifts and adds using canonical signed digit code (CSDC) technique. The proposed LWDFOI is implemented and successfully tested on Xilinx Spartan XC3s200-4ft256 field programmable gate array (FPGA) device. Simulation results are accomplished to show the comparison of the proposed LWDFOI with recent literature. The performance of the proposed LWDFOI is also evaluated in terms of speed, i.e. maximum frequency, area (number of slices) and power consumption. The proposed LWDFOI have been found to outperform the existing ones reasonably well in low and mid frequency range.