An asynchronous finite impulse response filter design for Digital Signal Processing circuit

摘要

The clockless feature of asynchronous circuit promotes its application in Digital Signal Processing (DSP) under special applications such as ultra-low power and extreme environments. In this paper, Finite Impulse Response (FIR) filter is implemented in delay-insensitivity asynchronous circuit using the pipeline architecture of Multi-Threshold NULL Conventional Logic (MTNCL). The computing units with different pipeline stages and pattern delay shift registers are integrated as 4 designs of FIR filter using the IBM 130nm 8RF process. Simulation results demonstrate the tradeoff between system throughput and energy efficiency, as the number of pipeline stage changes in the circuit.