Minimizing interposer warpage by process control and design optimization

摘要

An analytical model simulating the bowing at wafer or thin die level was applied to imec's 3D interposer technology. The calibration methodology is explained. A good correlation between simulation and measurement has been found at different stages during the processing. Secondly, a model combining all the interposer features was used to simulate the bowing induced at wafer and thin die level. Finally, the model is used to provide some recommendations to mitigate the interposer bowing without any drastic change in the structure or impact onto its performances.