IPSA: Integer Programming via Sparse Approximation for Efficient Test-Chip Design

摘要

Logic test chips are a key component of the yield learning process, which aim to investigate the yield characteristics of actual products that will be fabricated at high volume. Mathematically, the design of a logic test chip with such an objective may involve solving a constrained under-determined equation for an integer vector solution, which is unfortunately, NP-hard. Existing solving methods are not applicable due to lack of accuracy or high computational complexity. We propose a method called IPSA (Integer Programming via Sparse Approximation) to solve this integer programming (IP) problem in an effective and efficient manner. By solving a transformed sparse-regression problem and a subsequent rounding process, a solution can be achieved with comparable error to the optimal solution of the original IP problem but using far less time and memory. Experiments with seven industrial examples demonstrate that with more than 100× speed-up, IPSA achieves a similar or even better solution compared to directly solving the original problem with a commercial IP solver.