Combative cache efficacy techniques: Cache replacement in the context of independent prefetching in last level cache

摘要

The "memory wall" in CPU design refers to increasing divergence in performance growth between processors and memory. Prefetching and cache replacement were developed to overcome this, but there are few evaluations of the two techniques being used together. We contribute to this space by evaluating modern replacement policies in the context of a stride-N prefetcher. In exposing combative behavior between modern policies and the prefetcher, we hope to inform future design choices regarding such integration. Further, we present a means to either recoup or surpass performance gains seen in isolation for policies that exhibit conflict.