首页> 外文会议>Annual IEEE Applied Power Electronics Conference and Exposition >Design considerations for single-stage, input-current shapers for low output voltage ripple
【24h】

Design considerations for single-stage, input-current shapers for low output voltage ripple

机译:用于低输出电压纹波的单级输入电流成形器的设计考虑因素

获取原文
获取外文期刊封面目录资料

摘要

A lot of power topologies have been proposed to comply with the IEC-61000-3-2 regulations. One group of solutions involves obtaining an additional output from one of the converter's magnetic devices. These solutions are very good due to the low harmonic content and from the low cost point of view. Nevertheless these magnetic coupled circuits can modify the converter's performance. The abnormal operation can be observed as an output voltage ripple higher than expected. This paper deals with the design considerations for low output voltage ripple single-stage-input-current shapers (S/sup 2/ICS) and explains the abnormalities.
机译:已经提出了许多功率拓扑以遵守IEC-61000-3-2法规。一组解决方案涉及从转换器的磁器件中获得额外的输出。由于谐波含量低,并且从低成本的角度来看,这些解决方案非常好。然而,这些磁耦合电路可以改变转换器的性能。可以观察到异常操作,作为高于预期的输出电压纹波。本文涉及低输出电压纹波单级输入电流整形器的设计考虑因素(S / SUP 2 / IC)并解释了异常。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号