首页> 外文会议>Annual IEEE Applied Power Electronics Conference and Exposition >50-kW 1kV DC bus air-cooled inverter with 1.7 kV SiC MOSFETs and 3D-printed novel power module packaging structure for grid applications
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50-kW 1kV DC bus air-cooled inverter with 1.7 kV SiC MOSFETs and 3D-printed novel power module packaging structure for grid applications

机译:50-KW 1KV直流母线空气冷却逆变器,带1.7 kV SiC MOSFET和3D印刷新型电源模块包装结构,用于电网应用

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The traditional heatsink design technologies for forced air-cooling and power semiconductors with low junction temperatures have constrained the converters to be designed with massive heatsinks. The low power losses of WBG device technology and higher junction temperature operation over a wide operating range of power have not been fully utilized with liquid-cooled systems. The other major limitation has also been the traditional power module packaging “stack” approach with baseplate. This paper presents a novel power stage design which involves 1.7 kV silicon carbide (SiC) MOSFETs, a heatsink design with Genetic Algorithm (GA) and built using 3D printing technology, and a novel integrated modular power module for high power density. The air-cooled module assembly has a SiC MOSFET phase leg module with split high-side and low-side switches and a gate driver with cross-talk and short circuit protection functions. The heatsink design was modeled using a co-simulation environment with finite element analysis software and GA in MATLAB and COMSOL. The proposed concepts were verified and validated through experiments at each stage of development. The power stage was evaluated at 800V, 900 V, and 1kV for 20 kHz switching frequency and 50-kW load. The experimental results show that the CEC efficiency is 98.4 %. In addition to the efficiency, a power density of 75 W/in3was also achieved.
机译:具有低结温的强制空气冷却和功率半导体的传统散热器设计技术限制了转换器,以设计具有大规模散热器。 WBG器件技术的低功率损耗和在宽操作范围内的WBG设备技术和更高的结温操作尚未完全使用液冷系统。其他主要限制也是传统的电源模块包装“堆栈”方法,底板。本文介绍了一种新型功率级设计,涉及1.7 kV碳化硅(SiC)MOSFET,具有遗传算法(GA)的散热器设计,并使用3D打印技术建造,以及用于高功率密度的新型集成模块化电源模块。空气冷却模块组件具有SiC MOSFET相位腿模块,具有分开的高侧和低侧开关以及​​具有串扰和短路保护功能的栅极驱动器。使用具有有限元分析软件和Matlab和COMSOL的有限元分析软件和GA的共模仿真环境进行建模。通过在每个发展阶段的实验核实和验证所提出的概念。功率级以800V,900 V和1KV评估为20kHz开关频率和50kW负载。实验结果表明,CEC效率为98.4%。除了效率外,功率密度为75 W / in 3 也实现了。

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