A design of pipelined-parallel CABAC decoder adaptive to HEVC syntax elements

摘要

This paper proposes a pipelined-parallel CABAC decoder architecture adaptive to HEVC syntax elements. In order to obtain high throughput of CABAC decoding, we classify syntax elements into single bin and multi-bin. Further we exploit the context model forwarding in resolving data hazard from the context model update. In order to reduce the critical path delay, we would attempt to rearrange the working schedule of context model updater and renormalizer. The proposed architecture achieves a decoding performance of 0.981 bin/cycle (BQSquare_qp37) to 1.38 bin/cycle (BasketballPassall_qp0) and the proposed CABAC HW architecture is functionally verified in Xilinx Virtex-5 and Linux-based evaluation boards with HM-10.0.