Structured design to optimize the output power of stacked power amplifiers

摘要

An enhancement of an analytical algorithm to simplify and structure the design of stacked power amplifiers is presented in this work. This enhancement includes the calculation of passive networks, which compensate the parasitic capacitances of the transistors and thereby increase the distortion-free output power and the power added efficiency (PAE). As an example the algorithm is applied to a power amplifier (PA), using the IBM 180 nm CMOS process. The PA operates at 2GHz for the long term evolution (LTE) standard. The post-layout-simulation exhibits an output power in the 1 dB compression point of 28.2 dBm, leading to a PAE of 30%. The relative 3 dB bandwidth of the output power reaches a high value of 33%. The PA fulfills the specifications of LTE and therewith the high requirements on linearity.