data compression; decoding; discrete cosine transforms; industrial property; integrated circuit design; inverse transforms; program debugging; program verification; system-on-chip; video coding; HEVC decoders; IDCT; SoC; circuit size analysis; debugging capability; hardware IPs; hardware-software co-verification method; high efficient video coding; high performance digital systems; intellectual properties; inverse discrete cosine transform; operation speed; power consumption; system-on-chip; Decoding; Field programmable gate arrays; Hardware; IP networks; Software; System-on-chip; Video coding; HEVC decoder; IDCT IP; co-verification;
机译:硬件/软件协同验证:模型和方法
机译:Zynq上HEVC解码器的硬件 - 软件实现
机译:基于共享内存的FIFO HEVC解码器的高效系统级数据流程序硬件综合案例研究
机译:HEVC解码器的高效软硬件协同验证方法
机译:使用可重新配置的硬件实现节能的软硬件协同合成
机译:事后标记任意M / EEG记录可对神经解码方法进行数据有效评估
机译:用于硬件/软件协同验证的Büchi下推式系统的有效可达性分析