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FENICE: A FLEXIBLE, SCALABLE HIGH PERFORMANCE SATELLITE AIS RECEIVER

机译:费用:灵活,可扩展的高性能卫星AIS接收器

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The ESA-CGS co-funded FlexiblE inNovative AIS reCeiver prototypE (FENICE) project aims at developing a Satellite AIS receiver prototype, able to decode and detect the AIS messages transmitted by the ships covered by the Antenna FoV of an AIS LEO satellite, fully compatible with both existing and future AIS terrestrial transponders. The proposed implementation is fully flexible and covers both the case of on-ground and on-board processing, as well as the deployment of different antenna subsystems. The trade-off on-board versus on-ground processing was analysed through further verification of the complexity and performance of the two options. The design and development of the prototype allowed assessing in detail the performances and complexity of the receiver. A dedicated Test Bed, able to generate the required AIS signals, was also developed. An approach based on 3U cPCI COTS boards has been selected for prototype implementation. The architecture includes: - an RF-IF Module, composed by: o RF-IF Front-End (developed from scratch, hosting the Analog-to-Digital converters); o Digital I/O (based on CGS-proprietary general-purpose board, performing digital signal conditioning and buffering); o Radio Frequency Generator (providing Local Oscillators and master clocks). - a Digital Module, an FPGA Board equipped with target Virtex5 device (selected among those having a space-grade counterpart), for VHDL implementation of the advanced demodulation algorithms - a Host Computer, for prototype management and Test Bed interface. The assessment of the performance and complexity of the processing was achieved by implementing on target FPGA the enhanced algorithms and technologies originally proposed by ESA, and further improved during the FENICE project. Thanks to the innovative demodulation algorithms and architecture, FENICE demonstrated to outperform all the known space-based AIS receivers. Furthermore, the FENICE AIS P/L accommodation on board mini- and micro-satellite platforms has been explored, providing initial engineering budgets (mass, volume, power consumption) to support SAT-AIS system studies. The analysis considered different antenna subsystems, including the CGS-led VHF Miniaturized Antenna project under ESA ARTES 5.1 program. This paper provides an overview of the main achievements and results of the FENICE project for the several configurations analysed in terms of architecture, antenna subsystem and satellite platform. The results demonstrated that the FENICE receiver provides an excellent solution both in terms of signal processing and in terms of technology to cope with the extremely challenging C/I expected over the AIS channels as seen from the satellite.
机译:ESA-CGS共同资助的创新AIS接收原型(FENICE)项目旨在开发卫星AIS接收器原型,能够解码和检测由AIS LEO卫星的天线FoV覆盖的舰船发射的AIS消息,完全兼容与现有和未来的AIS地面转发器一起使用。所提出的实施方式是完全灵活的,并且涵盖了地面处理和车载处理的情况,以及不同天线子系统的部署。通过进一步验证这两种选择的复杂性和性能,分析了板载处理与地面处理之间的权衡。原型的设计和开发可以详细评估接收器的性能和复杂性。还开发了专用的测试台,能够生成所需的AIS信号。已选择一种基于3U cPCI COTS板的方法来实现原型。该架构包括:-RF-IF模块,由以下组件组成:o RF-IF前端(从头开发,托管模数转换器); o数字I / O(基于CGS专用通用板,执行数字信号调节和缓冲); o射频发生器(提供本地振荡器和主时钟)。 -一个数字模块,一个装有目标Virtex5器件的FPGA板(从具有空间级的Virtex5器件中选择),用于VHDL实施高级解调算法-主机,用于原型管理和测试床接口。通过在目标FPGA上实施ESA最初提出的增强算法和技术,可以实现对处理性能和复杂性的评估,并在FENICE项目中得到了进一步改进。由于创新的解调算法和架构,FENICE的性能优于所有已知的空基AIS接收器。此外,已经探索了微型和微型卫星平台上的FENICE AIS P / L舱位,提供了初始工程预算(质量,体积,功耗)以支持SAT-AIS系统研究。分析考虑了不同的天线子系统,包括ESA ARTES 5.1计划下的CGS领导的VHF微型天线项目。本文概述了FENICE项目的主要成就和成果,其中包括从架构,天线子系统和卫星平台方面分析的几种配置。结果表明,FENICE接收器在信号处理和技术方面均提供了出色的解决方案,以应对从卫星上看到的AIS信道上预期的极具挑战性的C / I。

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