This paper presents the operation of seven-level inverter at maximum switching frequency of 75 Hz using synchronous optimal pulsewidth modulation (SOP). Employing SOP permits increasing efficiency by reducing switching losses of power semiconductor devices without compromising on total harmonic distortion (THD). A cascade-5/3H inverter topology is adapted used due to limitations of diode-clamped and capacitor-clamped topologies for higher-level inverters. SOP technique derives optimal switching angles for minimizing the THD and later seven-level waveforms are divided into 3-level and 5-level waveforms for cascade-5/3H topology so as to minimize the switching frequency and DC-link voltage unbalance. Simulation results of seven-level inverter using PSIM 9.0 operating at maximum device switching frequency of 75 Hz are shown to validate the developed modulation.
展开▼
