A Synthesis Method to Alleviate Over-testing of Delay Faults Based on RTL Don't Care Path Identification

摘要

A register-transfer level (RTL) circuit meeting a design specification may contain some functionally unused paths. If functionally unused paths can be easily identified at RTL, the information can be utilized to eliminate the corresponding gate-level paths from the target of testing. Testing such gate-level paths is considered to be futile. In this paper, we present a method for identifying such functionally unused paths, called RTL don't care paths, using RTL information, and a method of synthesis for transforming the identified paths into untestable paths which will never do a mischief. As a result, our approaches contribute to identification of many untestable paths and reduction of over-testing.