Hardware support for decimal computer arithmetic is growing to meet the increasing user demands in many computer applications such that in the past decade some commercialized processors have been equipped with decimal hardware units and the latest IEEE standard for floating point arithmetic (IEEE-754-2008) has supported decimal representations and operations. In particular, the 10-bit densely packed encoding for compact storage of three decimal digits has been defined, which require pre and post conversions to make arithmetic operations and proper storage possible. In this paper, we offer the 10-bit radix-1000 (chiliad) encoding of three decimal digits that can be directly processed by decimal arithmetic operators. The 16-digit and 34-digit BCD operands (as defined in IEEE-754-2008) are converted to 54-bit and 114-bit chiliad operands, respectively. Following the practice of using word-wide binary adders for decimal operands with some off-the-critical-path correction logic, we device an adder architecture for intermediate chiliad operands. The same adders can be shared by the binary floating point units with the IEEE-754-2008 53-bit and 113-bit significands. The synthesis results show that the proposed scheme is more area and power efficient than the best previous method.
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