In advanced CMOS technology, Single Event Effects due to high energy particle may cause different types of electrical effects when crossing silicon: from small delay variations, to bit flips, until permanent damage. Quasi Delay Insensitive asynchronous circuits are the most immune to delay variations thanks to the use of Delay Insensitive codes, but can be very sensitive to bit flips since a Single Event Effect may corrupt the handshake protocol. This paper presents a design technique to mitigate Single Event Effect by adding temporal redundancy to Delay Insensitive codes. This multiple bit fault tolerant design technique is adaptable to any 1-of-N DI code, and is particularly well suited to asynchronous Networks-on-Chip. The proposed Temporally Redundant Delay Insensitive codes have been evaluated using a Single Event Effect digital fault characterization environment. The result shows better SEE tolerance and reduced area and performance impact.
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