GALS Design for On-chip Ground Bounce Suppression

摘要

With technology scaling into the deep sub-micron regime, the power supply and ground noise, which is introduced by the simultaneous switching activity in digital circuits, becomes a challenge for SoC and Networks-on-Chip (NoC) design. In this paper, analytical expressions of the magnitude of ground bounce for different gate switching ratios are derived. It is shown that, by spreading the switching activity, asynchronous circuits design contributes to the ground bounce suppression in two aspects: (1) a significant decrease in the switching current strength and (2) a slight increase in the on-chip intrinsic decoupling capacitance. In order to minimize the switching ratio in large-scale digital VLSI systems, the globally asynchronous locally synchronous (GALS) design is exploited for coarse-grained scheduling and spreading the gate switching over different local clock domains. Important design guidelines, including the GALS system partitioning and local clock modulation, are discussed. As a practical example, a 64-point pipelined SYNC/GALS FFT processor was implemented using the IHP 130-nm CMOS process. The measurements on the packaged chip demonstrate that, compared with the synchronous mode, around 40% reduction in the magnitude of ground bounce is achieved in the GALS mode.