Petri Net Dynamic Partial Reconfiguration in FPGA

摘要

The rigorous digital design of embedded Application Specific Logic Controllers starts from algorithm designed with concurrent hierarchical control interpreted Petri net and then implemented into FPGA. But, there could be required to have several contexts of work mode of such device. The classic design flows includes all contexts in one control algorithm together with switching handling. The design flow proposed in this paper uses feature of dynamic partial reconfiguration of new FPGA devices. There is proposed a way of design of a top level Petri net and subnets describing particular contexts and its connections. The rules of implementation are also formed.