In the DSP with VLIW architecture, significant amount of power is consumed during instruction fetching process. In this paper, a novel loop buffer mechanism is proposed based on the analysis of the loop features. In this mechanism, a loop buffer is established during the loop executing process by reusing the instruction buffer. Different operation modes for the two regions can be switched dynamically according to the requirement, by which means the instruction memory access times can be reduced, and the power of instruction memory access decreases. Meanwhile, the instruction fetching bandwidth can be used more effectively. The experiment results show that the program execution time and the instruction fetching power are reduced by 3.17% and 43.05% separately.
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